A successive approximation register analog-to-digital converter (SAR ADC) is capable of converting an analog signal into a digital signal. Referring to FIG. 1, the SAR ADC is formed of a comparator, a register and a digital-to-analog converter (DAC), the principle of converting the analog signal into the digital signal by the SAR ADC is: comparing an analog input signal with a reference signal which is provided by an output of a D/A converter (DAC), determining to increase or decrease the digital signal input to the DAC according to the comparison result such that the reference signal approximates to the analog input signal, and when the reference signal is equal to the analog input signal, the digital signal input to the DAC is the digital signal corresponding to the analog input signal. Thus, the analog-to-digital conversion can be implemented by means of successive approximation of the DAC output to the voltage of the analog input signal, and the process of the successive approximation may be referenced to FIG. 2.
The SAR ADC can be used as a key component for interfacing between an analog module and a digital module, and is extensively applied to mobile devices, wireless sensors and the like. Due to the size and battery life of the device, the analog-to-digital converter with small size and low power consumption is needed, such that the analog-to-digital converter can be conveniently integrated into the circuits of various devices.
Two types of DAC capacitor arrays applicable to the SAR analog-to-digital converter may be provided in the related art, as illustrated in FIG. 3 and FIG. 4 respectively.
FIG. 3 illustrates a conventional DAC capacitor array. Capacitors in the DAC capacitor array are not arranged in a binary weighting manner according to the capacitance values thereof. Each branch has the identical unit capacitor. Since the manufacturing error is proportional to the capacitance value and area of the capacitor, the manufacturing error may be reduced if the identical unit capacitors are employed. Relative to the capacitor arrays arranged in a binary weighting manner according to the capacitance values thereof, the size and power consumption of the entire capacitor array may be reduced when the identical unit capacitors are employed. However, this technical solution may have a problem that too many control branches are needed for the array, which may directly cause an increase of size and power consumption of the control circuit, the advantages achieved by reduction of the capacitor area are reduced or even disappear.
FIG. 4 illustrates another conventional DAC capacitor array. In the DAC capacitor array shown in FIG. 4, except two unit capacitors on the right side, the other capacitors are arranged in a binary weighting manner according to the capacitance values thereof. For the DAC capacitor array, the power consumption of the circuit may be effectively reduced by changing the reference voltage of the unit capacitors on the right side of the DAC capacitor array. However, if there are too many capacitors that are arranged in the binary weighting manner, the total capacitance may be very large, the power consumption of the circuit may be increased, or even power consumption reduction achieved by changing the reference voltage of the right-side unit capacitor may be offset.